发明名称 |
Advisory System for Verifying Sensitive Circuits in Chip-Design |
摘要 |
A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
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申请公布号 |
US2009172617(A1) |
申请公布日期 |
2009.07.02 |
申请号 |
US20080054195 |
申请日期 |
2008.03.24 |
申请人 |
HUANG CHI-HENG;LIN GARY;CHEN CHU-FU;CHENG YI-KAN;HSUEH FU-LUNG |
发明人 |
HUANG CHI-HENG;LIN GARY;CHEN CHU-FU;CHENG YI-KAN;HSUEH FU-LUNG |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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