| 摘要 |
A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal.
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