发明名称 |
Parallel multiplexing duty cycle adjustment circuit with programmable range control |
摘要 |
A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
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申请公布号 |
US7545190(B2) |
申请公布日期 |
2009.06.09 |
申请号 |
US20070742845 |
申请日期 |
2007.05.01 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
CHIANG MEEI-LING;MAHESHWARI SANJEEV;FANG EMERSON S. |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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