| 摘要 |
A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.
|
