| 摘要 |
PROBLEM TO BE SOLVED: To overcome the problem that the number of scan steps is increased and the effectiveness for reducing a scan path length by integrating scan chains using exclusive ORs is reduced regardless of a process using a masking method for preventing a value X from being inputted to the exclusive ORs if an expected value for a scan flip-flop is the uncertain value X although there is a technology for reducing the scan path length by integrating a plurality of the scan chains as a technology for compressing a scan pattern. SOLUTION: A semiconductor integrated circuit comprises: a plurality of the scan paths SP for implementing a LSI test; an output response compressor 20 for compressing output responses from a plurality of the scan paths; and an uncertain value propagation preventing circuit 2 inserted between an input side of a first stage of the scan flip-flops SF in a plurality of the scan paths and an uncertain value generating source 1 for generating the uncertain value while a test pattern is generated, and implementing a control for blocking a propagation of the uncertain value from the uncertain value generating source. The expected value X is prevented from being generated, and a degradation in a compression ratio is avoided. COPYRIGHT: (C)2009,JPO&INPIT
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