| 摘要 |
A semiconductor memory device includes: a termination resistance supply unit connected to a pad to supply termination resistances corresponding to a plurality of control signals; a decoding unit for decoding the plurality of ODT setting signals to output an ODT enable signal and a plurality of decoding output signals; a control signal generating unit for receiving the plurality of decoding output signals to output the plurality of control signals in response to an ODT off signal and a clock signal; and an output control unit for activating one of the plurality of control signals when a read enable detection signal is activated.
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