| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generation control circuit for reducing a load of a CPU. <P>SOLUTION: The clock generation control circuit is provided with: a counter for counting pulses of a clock signal outputted from an oscillation circuit for a prescribed period, and when the count value becomes equal to a set value corresponding to the prescribed period and a frequency, switching an output level of a count control signal; and an error detection circuit for detecting a timing error between a timing signal indicating the prescribed period and the count control signal and outputting an error detection signal. A frequency control circuit generates a control signal based on the error detection signal. <P>COPYRIGHT: (C)2009,JPO&INPIT |
