发明名称 Lowering resistance in a coreless package
摘要 In one embodiment, the present invention includes a coreless substrate to provide a power net connection and a ground net connection to a semiconductor die, which is electrically coupled to the substrate, and a stiffener surrounding the semiconductor die and electrically coupled to the substrate to provide a lateral current path to the semiconductor die. Other embodiments are described and claimed.
申请公布号 US2009001528(A1) 申请公布日期 2009.01.01
申请号 US20070823400 申请日期 2007.06.27
申请人 BRAUNISCH HENNING;LU DANIEL 发明人 BRAUNISCH HENNING;LU DANIEL
分类号 H01L23/552;H01L23/36 主分类号 H01L23/552
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