| 摘要 |
An address synchronous circuit including an address control signal generator and an address synchronization part is provided to contribute to a low power consumption of DRAM by reducing an unnecessary current consumption by a toggling of an inputted address. An address synchronous circuit comprises an address control signal generator(30) and an address synchronization part(40). The address control signal generator generates a control signal in response to an operating mode signal and an internal clock signal of a semiconductor memory. The address synchronization part controls an output of a buffered address by a clock enable signal.
|
