| 摘要 |
PURPOSE:To improve the reliability of a unit by performing processing with efficiency, by sending an instruction-retry disability signal only when the AND condition of a control memory fault detection signal and request signal to a memory and channel is met. CONSTITUTION:Output signals of parity checking circuits 6F and 6C for fields F and C of control memory read register 3 set control memory fault detection FF7F, 7C and through OR gate 14, control memory fault detection signal (f) is output. Next, this signal (f) and a signal from OR gate 10 performing OR of a request signal to a memory and channel are input to AND gate 11 and only when AND is established, an instruction retry disability signal is sent out. At the same time, the instruction retry processing is inhibited and unrecoverable fault generation interruption starts immediately. When this signal is not sent out, the instruction retry processing is performed as usual. |
