| 摘要 |
PURPOSE:To simplify the control over the thickness of the channel region as well as to obtain the J-FET of large mutual conductance for the titled transistor by a method wherein the diffusion process for connection is omitted, and the channel region is formed into a buried type structure. CONSTITUTION:A hole 11 of the size corresponding to the channel region is bored on the channel forming region of a p<+> type si substrate 10 by performing etching, an n type layer 12 which is thicker than the depth of the hole 11 is epitaxially grown on the whole surface including the hole 11. Then, the surface of the layer 12 is flattened by polishing, and the layer 12 is formed into the structure wherein it is buried into the substrate 10 as a channel 13. Subsequently, an SiO2 film 3 is deposited on the whole surface, the prescribed holes 5a and 5b are bored, and n<+> type source and drain regions 6a and 6b are formed in the region 13 by diffusion n type impurities in the holes 5a and 5b. Then, a hole 7 is bored again between holes 6a and 6b on the film 3, and a p<+> type source region 8 is formed here by diffusing p type impurities. Thus, the thickness of the channel region can be controlled accurately by polishing said region. |
