Processor comprising a file of addressable registers as several sets of registers contained in windows

摘要

A processor includes a file of addressable registers as sets each contained in a window. Each set possesses input registers (EN), local registers and output registers (SOR). Other registers are common to all the sets. The processor (20) furthermore comprises an arithmetic and logic unit (26) and a cache memory (28) forming the currently processed window and means for changing the addresses of lines of the cache memory (28) during saving and re-writing operations, so as to increase the speed of execution of the operations by the processor (20). Applicable to computers with reduced instruction set using an upgradeable process architecture (SPARC).