SEQUENTIAL PROGRAMMER

摘要

The invention concerns a sequential scheduling system.In accordance with this invention, the scheduling system consists of an oscillator connected to a dividing counter. The counter output is connected to a gate input and to a programmable dividing counter input. The output of the latter is connected by two validation gates to an address counter input. The address output of the counter is connected to a storage unit. The data output of the storage unit is connected to a channel amplifying unit. The output of the first gate is connected to the S input of a bistable trigger circuit. The bistable trigger circuit output is connected to the input of the second gate. A starting change-over switch is connected to the R input of a second bistable trigger circuit. A stop switch is connected to the S input of the same bistable trigger circuit. The output of this bistable trigger circuit is connected to the input of the first bistable trigger circuit and the input of a fourth gate. The output of a fifth gate is connected to the other input. The fifth gate has an input connected to the data bit from the output of a storage unit and the other input, to a RS circuit. The output of the fourth gate is connected to the input of the initial adjustment of the address counter of the dividing counter and programmable dividing counter.