发明名称 |
Fault-tolerant digital computing system with reduced memory redundancy |
摘要 |
A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.
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申请公布号 |
US5086429(A) |
申请公布日期 |
1992.02.04 |
申请号 |
US19900506714 |
申请日期 |
1990.04.10 |
申请人 |
HONEYWELL INC. |
发明人 |
GRAY, SCOTT L.;THOMPSON, STEVEN R. |
分类号 |
G06F11/00;G06F11/10;G06F11/16;G06F11/20 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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