| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of suppressing variation in transistor characteristics caused by the well proximity effect. SOLUTION: Standard cell lines 11, 12, 13, ... in each of which standard cells 10 are laterally disposed, are longitudinally disposed side by side. The standard cell lines 11, 12, 13, ... are flipped on every other line, the standard cell lines 11, 12 share a P region, and the standard cell lines 12, 13 share N wells. Distances D1, D2, D3 from PMOS transistors 21, 22, 23 positioned at the ends of the standard cell lines 11, 12, 13 to the end of the N wells are spread so as to be equal to or wider than a width W1 of the N wells shared by the standard cell lines 12, 13. COPYRIGHT: (C)2009,JPO&INPIT
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