| 摘要 |
<P>PROBLEM TO BE SOLVED: To remove factors that increase the semiconductor chip size in a CSP (Chip Size Package) type semiconductor device which adopts POE (Pad On Element) technique and staggered electrode pad arrangement. <P>SOLUTION: Adjacently to the corner cells 11 on the surface of a semiconductor chip 10, I/O cells 12 are formed so as to line up along the periphery, and electrode pads 13 are separately formed on the I/O cells 12. The electrode pads 13 constitute an inside pad arrangement and an outside pad arrangement so as to form the staggered pad arrangement. However, omitting the electrode pad arrangement in a prescribed range adjacent to the both sides of the corner cells 11 among the electrode pads 13 constituting the inside pad arrangement, complication of wiring patterns 21 of a carrier 20 which is bump-connected to the semiconductor chip 10, and via holes 22 is prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT |
