| 摘要 |
PROBLEM TO BE SOLVED: To provide a device and method for digital circuit verification, which processes assertions written in a property specification language capable of describing high-level specifications and specifications on IPs. SOLUTION: When a decision result of a temporal logic formula decision device is true, a verification program interpreting part is driven to execute a verification program paired with a temporal logic formula which gets true. The verification program interpreting part executes the verification program while driving a shared storage part holding values shared among all verification programs. COPYRIGHT: (C)2009,JPO&INPIT |
