| 摘要 |
PROBLEM TO BE SOLVED: To contribute to improvement of yield of products and reliability by enabling minute adjustment of timing of activation of wordlines of first and second ports during a test, by enabling a test in the worst case, and by improving accuracy of a test. SOLUTION: Timing control of activation of wordlines WLA, WLB of ports A, B are performed respectively based on clock signals (CLKA, CLKB), signals for test (TESTA, TESTB) are provided according to the clock signals (CLKA, CLKB) controlling respectively timing of activation of word lines of the ports A, B, TESYA is in an activation state in cells in which the ports A, B are selected, when TESTB is in a non activation state, the clock signal CLKB is masked and activation of the wordlines WLA, WLB of the ports A, B is controlled in response to the clock signal CLKA, further minute adjustment of timing difference (0 is included) of activation of the wordlines WLA, WLB of the ports A, B is performed by a signal from a terminal DLY. COPYRIGHT: (C)2009,JPO&INPIT
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