发明名称 METHOD OF ERASING CHARGE FROM ELECTRICAL PATH AND FLOATING GATE OF MEMORY CELL
摘要 PROBLEM TO BE SOLVED: To provide a heavily-doped buried layer that is implanted at a high energy in a lightly-doped separation well. SOLUTION: The buried layer 500 is doped with a dopant having the same conductivity as that of a well where the buried layer 500 is provided. The buried layer 500 reduces the size of a channel of a flash EPROM cell and achieves higher array density. A low resistance path is provided between the channels of the flash EPROM cell by the buried layer 500, thereby reducing the channel of the flash EPROM until erasure can be performed by giving the voltage (potential difference) between a gate line 28 and the substrate of the cell. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008270838(A) 申请公布日期 2008.11.06
申请号 JP20080170899 申请日期 2008.06.30
申请人 SPANSION LLC 发明人 LIU DAVID K Y;CHEN JIAN
分类号 H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
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