发明名称 IMAGE PROCESSING APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To provide an image processing apparatus which reduces the amount of data to be transferred on a bus, a plurality of image processes that cause increase in the memory capacity can be continuously performed and the plurality of image processes can be partially bypassed. <P>SOLUTION: In an image processing apparatus which is capable of performing reduction recording processing by using a YC generating circuit 5a, an LPF processing circuit 5b, a Cubic circuit 5c, non-magnification recording processing is performed by direct input from the YC generating circuit to a JPEG processing section 6, while bypassing a high-frequency cut LPF processing circuit and a resizing Cubic circuit. In that case, sticking tab data required for two processes to be bypassed are adjusted, and the width of a basic unit to be read from a frame memory is set. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2008263646(A) 申请公布日期 2008.10.30
申请号 JP20080169857 申请日期 2008.06.30
申请人 OLYMPUS CORP 发明人 UENO AKIRA;NAKAZONO KEISUKE
分类号 H04N5/232;G06T1/20;H04N5/228;H04N5/91;H04N101/00 主分类号 H04N5/232
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