发明名称 Circuit State Scan-Chain, Data Collection System and Emulation and Verification Method
摘要 The present invention provides a circuit state scan-chain for emulating and verifying integrated circuit design, a data collection system and an emulation and verification method using the scan-chain. The said integrated circuit includes a number of registers and the corresponding input terminal combinational logics and output terminal combinational logics. The construction of the said scan-chain includes the first multiplex module and the second multiplex module arranged with regard to each register, changing the operation mode of the said integrated circuit by controlling the first multiplex module and the second multiplex module, enabling the said integrated circuit to switch among the normal mode, holding mode and snapshot mode, and enabling the registers to form a scan-chain loop in the snapshot mode.
申请公布号 US2008250365(A1) 申请公布日期 2008.10.09
申请号 US20060067733 申请日期 2006.07.31
申请人 MAGIMA DIGITAL INFORMATION CO., LTD. 发明人 CHOU JEN-YA;ZHANG YA-LIN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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