| 摘要 |
PURPOSE:To perform unconditional disregard operation by an operator when a plant interlock condition of final control element is unestablished, by forming an OR circuit by making a condition disregard signal set to correspond to the final control element en block with the plant interlock condition of the final control element. CONSTITUTION:AND condition of plant interlock is decided by the plant interlock condition 3, and start and stop command of the final control element is outputted by the AND circuit of a final control element output processing means 4 through a condition disregard processing means 5 consisting of an OR circuit. When a part of plant interlock condition is not established by a condition deciding means 3, an operator sets the number of a condition disregard signal point set to correspond to the final control element. Thereby, the OR circuit of the processing means 5 receives a setting signal, and outputs start/stop command to final control element output through an output processing means 4. Thus, unconditional disregard operation by an operator when plant interlock condition of the final control element is not yet established becomes possible.
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