| 摘要 |
A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory ( 102 ), one or more processing loop modules ( 120 ), and an output buffer memory ( 112 ). Each processing loop module is comprised of a permutation module ( 110 ), inner decoding engines ( 202 <SUB>1</SUB>- 202 <SUB>N</SUB>); a depermutation module ( 106 ), and outer decoding engines ( 402 <SUB>1</SUB>- 402 <SUB>N</SUB>). The depermutation module is comprised of a concatenating device ( 304 ) and two or more depermutation buffer memories ( 306 <SUB>1</SUB>- 306 <SUB>N</SUB>). The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation. The permutation module is also comprised of a concatenating device ( 504 ) and two or more permutation buffer memories ( 506 <SUB>1</SUB>- 506 <SUB>N</SUB>). The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation.
|
