发明名称 |
Method of manufacturing an interconnection structure with air gaps for an integrated circuit |
摘要 |
<p>The method involves depositing a sacrificial material e.g. silicon dioxide, layer (11) on a substrate (10), and etching the layer according to a pattern corresponding to electrical conductors. A membrane layer made of permeable material is deposited on an etched surface of the material layer. The material is decomposed using an agent, where air cavities are formed at the decomposed material. The electric conductors, which are separated by the air cavities, are formed in the etched pattern. An electrically insulation material layer is deposited for covering interconnections.</p> |
申请公布号 |
EP1970950(A2) |
申请公布日期 |
2008.09.17 |
申请号 |
EP20080102290 |
申请日期 |
2008.03.05 |
申请人 |
COMMISSARIAT A L'ENERGIE ATOMIQUE |
发明人 |
GAILLARD, FREDERIC-XAVIER |
分类号 |
H01L21/768;H01L23/522;H01L23/532 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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