| 摘要 |
An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing: gate electrodes of the non volatile memory cells which comprise at least one first conductive layer, one first insulating layer, one second conductive layer and one third conductive layer and are insulated from the semiconductor substrate by means of a second insulating layer, gate electrodes of high voltage transistors which comprise the at least one first conductive layer whereon the third polysilicon layer is overlapped and is insulated from the semiconductor substrate by means of a third insulating layer of greater thickness than the second insulating layer, gate electrodes of low voltage transistors which comprise the second conductive layer whereon the third conductive layer is overlapped and are insulated from the semiconductor substrate by means of a fourth insulating layer.
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