Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks

摘要

A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a plurality of sensitization conditions associated with one or more clock signals in a circuit network operable in a plurality of modes and automatically eliminating false paths from a plurality of clock paths of the circuit network based on the plurality of sensitization conditions. Other embodiments have been claimed and described.