STACKED BANK MEMORY CAPABLE OF HIGH SPEED

摘要

A stacked bank memory capable of high speed operation is provided to increase memory access speed by changing position of a Y-decoder and a main sense amplifier. A memory has a first pad(408) and a second pad(410). The first pad receives an address and a control signal from a processor and the second pad inputs/outputs data. According to the memory, a plurality of banks(400-406) are stacked. An X-decoder(424) enables a word line included in the banks through the row address and the control signal received from the first pad. A Y-decoder(426) enables a column selection line corresponding to a memory cell connected to the enabled word line through the column address and the control signal from the first pad. A main sense amplifier is arranged at the opposite side of the Y-decoder, and performs amplification to write or read data to/from the memory cell.