| 摘要 |
In a CML to CMOS clock signal convener and correction circuit, small-signal differential CML clock signals INA,INB are received by a differential amplifier 802 which drives two CMOS output buffers 804,806. Each output buffer has a control loop which controls the mark-space ratio of the output signals OUTA, OUTB to 50%. Clock convener and correction circuits of this form may be used to produce two sets of antiphase signals, the signal sets being in quadrature, for an XOR/XNOR frequency doubler circuit (figure 10). The two sets of clock signals are maintained in quadrature by a feedback control circuit (708, figure 7) acting in opposing fashion on the current sources 812 of the two clock conversion and correction circuits (702,704). |
