| 摘要 |
<p>A method for manufacturing a non-volatile memory device is provided to improve the reliability of the non-volatile memory device by reducing erasion fail of the non-volatile memory device. A cell region including a drain selection transistor and a source selection transistor and a peripheral circuit region including a plurality of transistors are defined on a substrate. A first interlayer dielectric is formed on an upper surface of the substrate including memory cells. A metal contact connected to a junction region of the source selection transistor, junction regions of the transistors, and gate electrodes of the transistors is formed within the first interlayer dielectric(S102,S104). A second interlayer dielectric is formed on the first interlayer dielectric(S106). A drain contact plug connected to the junction region of the drain selection transistor is formed within the first and second interlayer dielectrics of the cell region(S107).</p> |
