| 摘要 |
A PLL frequency synthesizer improves near C/N, shortens lockup time, and reduces residual FM. In this apparatus, an input current signal is converted to a voltage signal by one of a plurality of loop filters with different cutoff frequencies and output to a voltage controlled oscillator. An oscillation signal generated by the voltage controlled oscillator is branched at a first junction point and output to a frequency divider and an output terminal. A variable capacitance capacitor is connected to a second junction point branched subsequent to the first junction point and its capacitance is controlled in accordance with loop filter switching control of a control circuit.
|
