发明名称 LAZY SCHEDULING FOR LDPC DECODING
摘要 <p>A decoder, of a codeword representation that includes a plurality of soft bits, includes a plurality of functional modules for updating the soft bits iteratively. Whether each soft bit participates in at least some iterations is determined according to a selection criterion, e.g., probabilistically, or according to iteration number, or according to the soft bit's iteration history. For example, each soft bit might participate in some or all iterations with a probability that is a function of both the iteration number and a reliability measure of that soft bit. Preferably, the functional modules are LDPC functional modules that address variable nodes sequentially for exchanging messages with corresponding check nodes. The decoder may be implemented in circuitry of a memory, in a controller of a memory device, or in a host of a memory device.</p>
申请公布号 WO2008075337(A1) 申请公布日期 2008.06.26
申请号 WO2007IL01528 申请日期 2007.12.11
申请人 RAMOT AT TEL AVIV UNIVERSITY LTD.;SHARON, ERAN;LITSYN, SIMON 发明人 SHARON, ERAN;LITSYN, SIMON
分类号 H03M13/11 主分类号 H03M13/11
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