| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce an excess region on a chip plane and to reduce a chip size. <P>SOLUTION: A plurality of data pads 22a for inputting and outputting data are arranged near one side of the outer periphery of a substrate 20 along the one side, and a plurality of data pads 22b for inputting and outputting the data are disposed along the plurality of data pads 22a on the inner side. NMOSes 28a and 28b for outputting the data are disposed between the data pads 22a and 22b, and PMOSes 27a and 27b for outputting the data are disposed at positions facing the NMOSes 28a and 28b near the data pads 22a and 22b. <P>COPYRIGHT: (C)2008,JPO&INPIT |
