| 摘要 |
A conditional select adder having a carry generating unit which generates a carry of two n-bit input data units X<SUB>0</SUB>-X<SUB>n-1</SUB>, and Y<SUB>0</SUB>-Y<SUB>n-1</SUB>, and a sum generating unit which generates the sum of the input data, is provided. The carry generating unit comprises a first input unit which receives predetermined data based on the input data X<SUB>i </SUB>and Y<SUB>i</SUB>; a second input unit which receives the initial carry; and a selection unit which receives the result of performing an XOR operation on the input data X<SUB>i </SUB>and Y<SUB>i</SUB>, in which according to the XOR result, either predetermined data based on the input data X<SUB>i </SUB>and Y<SUB>i </SUB>input to the first input unit, or the initial carry input to the second input unit is selected and output as a carry. The sum generating unit calculates a sum using the carry generated by the carry generating unit. Advantages include reducing power consumption, chip area, logic count, and delay time.
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