| 摘要 |
A memory cell with a trigger element is provided to decrease a leakage current related with unselected bit lines, without maintaining a word line as a high level during total access period. According to a memory device, a plurality of word lines(26) are extended in rows and a plurality of bit lines(22) are extended in columns. A memory cell is coupled between the word line and the bit line, and the memory cell includes a unipolar memory element(21) selectively coupled to the bit line through a trigger element(24). The trigger element includes a thyristor coupled to the word line. The thyristor couples the unipolar memory element to the bit line through each word line when a pulse is applied to a gate of the thyristor, and the cycle of the pulse is shorter than the access cycle of the memory cell.
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