| 摘要 |
1. A flip-flop circuit including: a pulse generation circuit that receives a clock signal and outputs an internal clock signal; and a latch circuit, wherein the latch circuit includes: an input section that receives a data signal and the internal clock signal, outputs a signal of a second logic level to a first node when the internal clock signal is at a first logic level, and outputs a signal of logic depending on a logic level of the data signal to the first node after the internal clock signal changes from the first logic level to the second logic level; a control section that outputs a signal of the second logic level to a second node when the internal clock signal is at the first logic level, and outputs a signal of logic depending on a logic level of the first node to the second node when the internal clock signal is at the second logic level; and an output section that outputs a signal of logic depending on a logic level of the first node and/or a logic level of the second node, and wherein the pulse generation circuit changes the internal clock signal from the first logic level to the second logic level in response to a change of the clock signal from a third logic level to a fourth logic level and changes the internal clock signal from the second logic level to the first logic level in response to a change of the first node or the second node from the second logic level to the first logic level.
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