发明名称 Techniques for calibrating on-chip termination impedances
摘要 A calibration circuit block includes a first resistor network, a second resistor network, and a feedback loop. The first resistor network includes a set of transistors and receives a constant current from a constant current source. The second resistor network receives a tracking current from a tracking current source. The impedance of the second resistor network changes with temperature and process variations on the integrated circuit. The tracking current source compensates for variations in the impedance of the second resistor network that are caused by process and temperature variations to maintain a constant reference voltage at the second resistor network. The feedback loop generates calibration control signals for controlling the conductive states of the transistors in the first resistor network. The feedback loop adjusts the calibration control signals to maintain a constant impedance in the first resistor network.
申请公布号 US7372295(B1) 申请公布日期 2008.05.13
申请号 US20060615579 申请日期 2006.12.22
申请人 ALTERA CORPORATION 发明人 WEI KWONG-WEN
分类号 H03K19/003 主分类号 H03K19/003
代理机构 代理人
主权项
地址