WAFER LEVEL CHIP SCALE PACKAGE

摘要

A wafer level chip scale package is provided to reduce bending of a semiconductor chip by selectively forming an insulating layer only on a portion which is required for electrical connection of the semiconductor chip. An insulating layer(22) is selectively formed on a semiconductor substrate(21) having bonding pads to comprise only a region, in which a rewiring layer(24) is formed. The rewiring layer is formed on the insulating layer and electrically connected to the bonding pad of the semiconductor chip exposed from the insulating layer. A solder mask(23) is formed on the rewiring layer to form a ball land(25) to attach a mounting member.