| 摘要 |
<p>A transistor and a memory cell array are provided to obtain optimal characteristics of an access transistor, and manufacture a DRAM memory cell array having high packaging density in a simple process. An integrated circuit includes a transistor formed within a semiconductor substrate(1) having an upper surface(10). The transistor comprises a first and a second source/drain regions(51,52), a channel(23), a gate groove, and a gate electrode(27). The channel connects the first source/drain region and the second source/drain region with each other, comprising a fin-like portion in the shape of a ridge which has an upper side and two lateral sides at a cross-section crossing with a first direction, wherein the first direction is defined by a line that connects the first and second source/drain regions with each other. The gate groove defined on the upper surface of the semiconductor substrate, comprising an upper groove portion and a lower groove portion, wherein the groove portions are filled with an insulating material. The gate electrode is disposed in the lower groove portion, surrounding the channel from the upper side of the channel and two lateral sides.</p> |
