发明名称 |
SIMULATION MODEL OF BT INSTABILITY OF TRANSISTOR, AND SIMULATION MODELING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a simulation model of BT (Bias Temperature) instability of a transistor with a proper evaluation level without leading to an excess in evaluation and quality. SOLUTION: In this simulation model of BT instability of a transistor, a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2008053692(A) |
申请公布日期 |
2008.03.06 |
申请号 |
JP20070167655 |
申请日期 |
2007.06.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
KINOSHITA MITSUNARI;ISHIZU TOMOYUKI |
分类号 |
H01L21/336;G06F17/50;H01L29/00;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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地址 |
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