METHOD FOR PROTECTING AN ALIGNMENT MARK

摘要

A method for protecting an alignment mark is provided to reduce damage of an alignment mark and to increase a yield of semiconductors by increasing a thickness of a cap oxide layer. An interlayer dielectric(202) is formed on a semiconductor substrate(200) having an alignment mark(200a). The interlayer dielectric is planarized by performing a CMP(Chemical Mechanical Polishing) process. A cap oxide layer(204) is thickly formed on the interlayer dielectric in comparison with a process thickness. A via hole(A) is formed by etching partially the interlayer dielectric and the cap oxide layer. A metal layer is formed to bury fully the via hole. The cap oxide layer is removed and a via contact is formed by performing a CMP process using a polishing stop point of the interlayer dielectric.