| 摘要 |
A shift register has a plurality of stages which output driving signals, each stage including a pull-up transistor to output a first clock signal in response to a logic value of a Q node; a pull-down transistor to supply a voltage from a first voltage supply source to the output in response to a logic value of a Qb node; a Q node controller to control the logic value of the Q node in response to any one of the previous stage's output signal and the next stage's output signal; and a Qb node controller to control the logic value of the Qb node to alternate repeatedly between low and high by use of at least one of a second clock signal, a third clock signal and the logic value of the Q node when the output signal is in a low state.
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