A plasma display panel is provided to lower a discharge voltage by reducing a jitter value of an address period and obtaining a high secondary electron coefficient value. A scan electrode(102) and a sustain electrode(103) are formed on an upper surface of a front substrate(101). A dielectric layer(104) is formed to cover the scan electrode and the sustain electrode. A protective layer(105) is formed on the dielectric layer. The protective layer is formed of MgO as a main component. A partial region of the protective layer is doped with silicon. The partial region of the protective layer doped with silicon corresponds to 1/3 to 1/4 of the thickness of the protective layer. The silicon doped on the partial region of the protective layer is 400-900 ppm.
