| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the load of a CPU by solving the problem that processing quantity to be shared by the CPU is large since when a TS packet is received in the middle, it is detected as an error, and error detection processing is performed by a processor(CPU) which performs decoding processing or the like in a digital broadcasting receiver. <P>SOLUTION: This information processor is mounted with a digital broadcasting receiver equipped with an error detection circuit 20 having at least one of a synchronizing byte detection circuit 21, a synchronizing byte comparator circuit 23, and an error display comparator circuit 24 for receiving digital information to be transmitted by packet data by a digital tuner part 12, and for detecting the error of the packet data having any flaw in the successively received packet data from the interval of synchronizing bytes, the values of the synchronizing bytes or the values of error display for reproducing information from packet data from which the packet data having any flaw are removed. <P>COPYRIGHT: (C)2008,JPO&INPIT |
