发明名称 CLOCK SWITCHING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To prevent the generation of hazard in switching a clock signal, and to arbitrarily set a timing of switching a clock signal. <P>SOLUTION: Setting signals for setting the periods of stopping the output of a first clock signal and a second clock signal are generated from a clock selection signal for selecting a clock signal and a reference clock signal, and when the first clock signal is switched to the second clock signal based on these setting signals, a period to inhibit output of the clock signal is set. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008005279(A) 申请公布日期 2008.01.10
申请号 JP20060173554 申请日期 2006.06.23
申请人 D & M HOLDINGS INC 发明人 FUKUSHIMA MITSUGI
分类号 H04L7/00;G06F1/06;H03K5/00;H03K17/00;H03K19/0175;H04L7/02 主分类号 H04L7/00
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