发明名称 |
PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER |
摘要 |
Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
|
申请公布号 |
US2008007310(A1) |
申请公布日期 |
2008.01.10 |
申请号 |
US20070857632 |
申请日期 |
2007.09.19 |
申请人 |
AUSTIN JOHN S;KELKAR RAM;THIAGARAJAN PRADEEP |
发明人 |
AUSTIN JOHN S.;KELKAR RAM;THIAGARAJAN PRADEEP |
分类号 |
H03K3/289;H03L7/23 |
主分类号 |
H03K3/289 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|