发明名称 |
DCC CIRCUIT AND DLL CIRCUIT WITH DCC |
摘要 |
A DCC(Duty Cycle Correction) circuit and a DLL(Delay Locked Loop) circuit using the same are provided to prevent the generation of an internal clock not reflecting the variation of inner delay factor generated by external influence like power supply voltage variation. A clock input part generates a first and a second internal clock signal by receiving a first and a second clock input signal and an enable signal, from the first clock signal and an inversion signal thereof when the enable signal is enabled. A duty cycle mixing part(300) mixes phases of the first and the second internal clock signal.
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申请公布号 |
KR20080001432(A) |
申请公布日期 |
2008.01.03 |
申请号 |
KR20060059881 |
申请日期 |
2006.06.29 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM, SU HYUN;YOU, MIN YOUNG |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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