| 摘要 |
PROBLEM TO BE SOLVED: To reduce the possibility of disturbing a user by quickly reading/executing a program by a CPU and avoid a defect due to waiting until the CPU starts reading/execution of the program. SOLUTION: An ASIC 10 has a bus controller part 45 for sorting access requests from the CPU 12 to either of first to third buses B1 to B3. Based on the results detected by a ROM access frequency detection part 18 and a RAM access frequency detection part 20, the bus controller part 45 determines the state of a request memory (one of ROM 50 and RAM 55). When the request memory is not busy, the bus controller part executes access without changing an object to be accessed. When the request memory is busy, only when a non-request memory is not busy, the object to be accessed is changed from the request memory to the non-request memory. COPYRIGHT: (C)2008,JPO&INPIT
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