发明名称 Optimized DFT implementation
摘要 The present invention relates to a method and apparatus for implementing a discrete Fourier transformation (DFT) of a predetermined vector size, wherein at least one DFT module is configured to perform DFTs of a first predetermined number and of a vector size corresponding to a second predetermined number, to multiply by twiddle factors, and to perform DFTs of said second predetermined number and of a vector size corresponding to said first predetermined number. At least two of the at least one DFT module are combined to obtain the predetermined vector size. Thereby, an implementation of non 2<SUP>x</SUP>-radix Fourier transformation can be achieved with moderate hardware complexity.
申请公布号 US2007299903(A1) 申请公布日期 2007.12.27
申请号 US20060526122 申请日期 2006.09.25
申请人 NOKIA CORPORATION 发明人 XU YUHUAN;SCHWOERER LUDWIG
分类号 G06F7/52 主分类号 G06F7/52
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