发明名称 |
Junction leakage reduction in SiGe process by tilt implantation |
摘要 |
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a stressor in the semiconductor substrate adjacent to an edge of the gate electrode; and tilt implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
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申请公布号 |
US2007298557(A1) |
申请公布日期 |
2007.12.27 |
申请号 |
US20060607326 |
申请日期 |
2006.12.01 |
申请人 |
NIEH CHUN-FENG;KU KEH-CHIANG;CHEN CHIEN-HAO;CHANG HSUN;WANG LI-TING;LEE TZE-LIANG |
发明人 |
NIEH CHUN-FENG;KU KEH-CHIANG;CHEN CHIEN-HAO;CHANG HSUN;WANG LI-TING;LEE TZE-LIANG |
分类号 |
H01L21/8234 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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地址 |
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