| 摘要 |
A multi-bit memory cell ( 200 ) with a control gate ( 220 ) for controlling a middle portion of a channel region ( 208 ) provides improved operation including faster programming at smaller voltages and currents. The memory cell ( 200 ) includes a source ( 204 ) and a drain ( 206 ) diffused into a substrate ( 202 ) forming a channel region ( 208 ) therebetween. A first charge storing layer ( 214 ), a second charge storing layer ( 216 ) and the control gate ( 220 ) are formed on the substrate ( 202 ) over the channel region ( 208 ) and a gate ( 218 ) is formed over the source ( 204 ), the drain ( 206 ), the first and second charge storing layers ( 214, 216 ) and the control gate ( 220 ). Dielectric material ( 210, 212, 224, 226, 228 ) separates the source ( 204 ) and the drain ( 206 ) from the gate ( 218 ), and the control gate ( 220 ) from the first charge storing layer ( 214 ), the second charge storing layer ( 216 ) and the gate ( 218 ).
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